Flash memory is a common type of non-volatile memory. Flash memory cells may include a source region and a drain region that is spaced apart from the source region by an intermediate channel region. A memory cell, including a charge structure (e.g., a floating gate, a charge trap, or other similar structure), is disposed over the channel region and is electrically isolated from the other elements by a dielectric material, such as an oxide. For example, a tunnel dielectric material (which may also be referred to in the art as a “gate dielectric” material) may be disposed between the charge structure and the channel region. A control gate, of the memory cell, is located over the charge structure. The control gate may be electrically separated from the charge structure by a charge block region, such as another dielectric layer that may be referred to in the art as an “inter-poly dielectric” (IPD), an “intergate insulator,” or an “intergate dielectric.” Thus, the charge structure may be configured as a floating gate that is electrically “floating” so that it is insulated from both the channel and the control gate.
Fabricating memory cells often involves patterning a conductive material of the control gate region before patterning a conductive material of the charge structure region. After patterning the control gate region, but before patterning the charge structure region, a liner may be formed on the conductive material of the control gate region to provide protection to the conductive material during the latter (i.e., “subsequent”) patterning process in which the conductive material of the charge structure region is patterned. Nonetheless, conventional liners may not survive the subsequent patterning process and, as such, may leave at least partially exposed the conductive material of the control gate region. The exposure may result in damage to the conductive material of the control gate region. The damage may be in the form of any one of roughened sidewalls, undercuts at interfaces with neighboring regions, and decreased widths relative to the initially-patterned control gate region. This damage may result in degraded performance (e.g., increased resistance and capacitance) of the resulting memory cell. Thus, fabricating memory devices, including flash memory devices, without degradation to performance is often a challenge.